Modeling and Verification of 3-Dimensional Resistive Storage Class Memory with High Speed Circuits for Core Operation
暂无分享,去创建一个
Seongguk Kim | Joungho Kim | Subin Kim | Kyungjun Cho | Shinyoung Park | Gapyeol Park | Taein Shin | Kyungjune Son | Joungho Kim | Kyungjun Cho | Subin Kim | Shinyoung Park | Gapyeol Park | Kyungjune Son | Seongguk Kim | Taein Shin
[1] Subin Kim,et al. Modeling and Signal Integrity Analysis of 3D XPoint Memory Cells and Interconnections with Memory Size Variations During Read Operation , 2018, 2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI & PI).
[2] David A. Patterson,et al. Computer Architecture: A Quantitative Approach , 1969 .
[3] Bing Chen,et al. A SPICE Model of Resistive Random Access Memory for Large-Scale Memory Array Simulation , 2014, IEEE Electron Device Letters.
[4] Chaitali Chakrabarti,et al. Hierarchical modeling of Phase Change memory for reliable design , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).
[5] G.H. Koh,et al. Future memory technology including emerging new memories , 2004, 2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716).