Sneak-path Testing of Memristor-based Memories

Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in memristors and develop efficient fault models. Next, the memory subsystem has to be tested. The typical approach to testing a memory subsystem entails testing one memory element at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak-paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by ~32%.

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