Single-chip FIR adaptive filter using CMOS analog circuits

The design, simulation and testing results for a sampled-data analog adaptive filter are presented. The system uses clocked sampled-data storage, unique area-efficient analog multipliers, and other opamp-based arithmetic modules. The fully analog CMOS design features a non-multiplexed parallel architecture for achieving fast sampling rates and easy extension to higher order filters. The prototype chip was fabricated using 2- mu CMOS P-WELL technology, occupying an area of 4.0 mm/sup 2/, and using +or-5 V power supplies.<<ETX>>