Low Power and Area Efficient Carry Select Adder

In the field of electronics, adder is a digital circuit that performs addition of numbers. To perform quick arithmetic operations and functions, carry select adder (CSLA) is one of the quickest adder used in many data processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate - level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Modified Carry select adder (MCSLA), Regular Square Root CSLA (SQRT CSLA), Modified SQRT CSLA and Proposed SQRT CSLA in terms of area, delay and power consumption. The result analysis shows that the proposed structure is better than the conventional CSLA. Carry select adder (CSLA) is one of the fastest adder in comparison to all other adders. This review undergoes very simple and efficient gate-level modification to reduce the area and delay of the CSLA. Based on this modification, 8-bit, 16-bit, 32-bit and 64-bit Square-Root CSLA (SQRT CSLA) architecture have been developed having comparison with the regular SQRT CSLA architecture. The proposed circuit design has reduced area and delay as compared with the regular SQRT CSLA.

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