Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration

Bridging and interconnect open faults are defined using subsets of lines. We study the possibility of identifying input vectors that are effective as test vectors for such faults without enumerating the faults. This process does not require accurate layout information, it can handle very large numbers of faults, and it deals with undetectable faults implicitly. We describe a static test compaction process that uses the ability to identify effective test vectors without enumerating faults. This process selects a subset T of a given test set U such that T is guaranteed to detect the same faults as U. We also describe a test generation process based on the same concept. Finally, we show how this concept can be used to compare test sets.

[1]  Wojciech Maly,et al.  Testing oriented analysis of CMOS ICs with opens , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[2]  Bernd Becker,et al.  Resistive Bridge fault model evolution from conventional to ultra deep submicron , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[3]  Sandip Kundu,et al.  On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits , 2008, 2008 Design, Automation and Test in Europe.

[4]  Michel Renovell,et al.  Testing for floating gates defects in CMOS circuits , 1998 .

[5]  Víctor H. Champac,et al.  Detectability conditions for interconnection open defects , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[6]  R. D. Blanton,et al.  Multiple-detect ATPG based on physical neighborhoods , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[7]  F. Joel Ferguson,et al.  An unexpected factor in testing for CMOS opens: the die surface , 1996, Proceedings of 14th VLSI Test Symposium.

[8]  Michele Favalli,et al.  Fault simulation of parametric bridging faults in CMOS IC's , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Irith Pomeranz,et al.  Compact test sets for high defect coverage , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  D. M. H. Walker,et al.  Resistive bridge fault modeling, simulation and test generation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[11]  Venkatram Krishnaswamy,et al.  A study of bridging defect probabilities on a Pentium (TM) 4 CPU , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[12]  Daniel Arumí,et al.  Defective behaviours of resistive opens in interconnect lines , 2005, European Test Symposium (ETS'05).

[13]  R. Rodriguez-Montanes,et al.  Electrical and topological characterization of interconnect open defects , 2005, Proceedings. 2005 IEEE International Workshop on Current and Defect Based Testing, 2005. DBT 2005..

[14]  Irith Pomeranz,et al.  Test vector chains for increasing the fault coverage and numbers of detections , 2009, IET Comput. Digit. Tech..

[15]  Sandip Kundu,et al.  Defect-Based Test : A Key Enabler for Successful Migration to Structural Test , 1999 .

[16]  Michel Renovell,et al.  Electrical analysis and modeling of floating-gate fault , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Siyad C. Ma,et al.  A comparison of bridging fault simulation methods , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[18]  Irith Pomeranz,et al.  Forming N-detection test sets without test generation , 2007, TODE.

[19]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[20]  Haluk Konuk.  Voltage- and current-based fault simulation for interconnect open defects , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Robert C. Aitken,et al.  Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds , 1993, Proceedings of IEEE International Test Conference - (ITC).