A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias

We propose a new 2T mask ROM with dynamic column source bias control technique, which allows us to achieve both high-speed operation and low-power consumption. One can also overcome the inherent problem of the cross-talk noise between bitlines. The fabricated 128-kb ROM macro using 28-nm high-k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at 0.85 V, which is comparable with recent high-speed embedded SRAMs. Measured active power dissipation is 0.5× smaller than conventional 2T ROM. The standby leakage also can be reduced to a half of the conventional macros.

[1]  Koji Ohno,et al.  A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[2]  S. Yoshioka,et al.  A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU , 2009, IEEE Journal of Solid-State Circuits.

[3]  Kaushik Roy,et al.  A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Lee-Sup Kim,et al.  A low-power ROM using single charge-sharing capacitor and hierarchical bit line , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  David Blaauw,et al.  Robust ultra-low voltage ROM design , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[6]  Steven Eustis.  An embedded read only memory architecture with a complementary and two interchangeable power/performance design points , 2004, IEEE International SOC Conference, 2004. Proceedings..

[7]  Meng-Fan Chang,et al.  A full code-patterns coverage high-speed embedded ROM using dynamic virtual guardian technique , 2006, IEEE Journal of Solid-State Circuits.