Architecture and analysis of a dynamically-scheduled real-time memory controller

Memory controller design is challenging as mixed time-criticality embedded systems feature an increasing diversity of real-time (RT) and non-real-time (NRT) applications with variable transaction sizes. To satisfy the requirements of the applications, tight bounds on the worst-case response time (WCRT) of memory transactions must be provided to RT applications, while the lowest possible average response time must be given to the remaining applications. Existing real-time memory controllers cannot efficiently achieve this goal as they either bound the WCRT by sacrificing the average response time, or cannot efficiently support variable transaction sizes. In this article, we propose to use dynamic command scheduling, which is capable of efficiently dealing with transactions with variable sizes. The three main contributions of this article are: (1) a memory controller architecture consisting of a front-end and a back-end, where the former uses a TDM arbiter with a new work-conserving policy and the latter has a dynamic command scheduling algorithm that is independent of the front-end, (2) a formalization of the timings of the memory transactions for the proposed algorithm and architecture, and (3) an analysis of WCRT for transactions to capture the behavior of both the front-end and the back-end. This WCRT analysis supports variable transaction sizes and different degrees of bank parallelism. The critical part of the WCRT is the worst-case execution time (WCET) of a transaction, which is the time spent on command scheduling in the back-end. The WCET is bounded by two techniques applied to both fixed and variable transaction sizes, respectively. We experimentally evaluate the proposed memory controller and compare to an existing semi-static approach. The results demonstrate that dynamic command scheduling significantly outperforms the semi-static approach in the average case, while it performs equally well or better in the worst-case with only a few exceptions. The former reduces the average response time for NRT applications, and the latter pertains the WCRT for RT applications.

[1]  Kees G. W. Goossens,et al.  A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications , 2011, Des. Autom. Embed. Syst..

[2]  Björn Andersson,et al.  Response Time Analysis of COTS-Based Multicores Considering the Contention on the Shared Memory Bus , 2011, 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications.

[3]  C.H. van Berkel,et al.  Multi-core for mobile phones , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[4]  Kees G. W. Goossens,et al.  Architecture and optimal configuration of a real-time multi-channel memory controller , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[5]  K. B. Akesson,et al.  Memory-map selection for firm real-time memory controllers , 2012 .

[6]  Wang Yi,et al.  Building timing predictable embedded systems , 2014, ACM Trans. Embed. Comput. Syst..

[7]  Todd M. Austin,et al.  SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.

[8]  Wei-Fen Lin,et al.  Reducing DRAM latencies with an integrated memory hierarchy design , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[9]  Kees G. W. Goossens,et al.  A reconfigurable real-time SDRAM controller for mixed time-criticality systems , 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[10]  Kees G. W. Goossens,et al.  Conservative open-page policy for mixed time-criticality memory controllers , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[11]  Kees G. W. Goossens,et al.  Predator: A predictable SDRAM memory controller , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[12]  Henrik Theiling,et al.  Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement , 2014, 2014 26th Euromicro Conference on Real-Time Systems.

[13]  Calvin Lin,et al.  Memory scheduling for modern microprocessors , 2007, TOCS.

[14]  Bruce Jacob,et al.  Memory Systems: Cache, DRAM, Disk , 2007 .

[15]  Kees G. W. Goossens,et al.  dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up , 2014, IEEE Transactions on Computers.

[16]  Kees G. W. Goossens,et al.  A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels , 2015, TECS.

[17]  Rolf Ernst,et al.  Bounding the shared resource load for the performance analysis of multiprocessor systems , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[18]  Premysl Sucha,et al.  An efficient configuration methodology for time-division multiplexed single resources , 2015, 21st IEEE Real-Time and Embedded Technology and Applications Symposium.

[19]  Kees G. W. Goossens,et al.  Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[20]  Kees G. W. Goossens,et al.  A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[21]  Tomas Henriksson,et al.  Heterogeneous multi-core platform for consumer multimedia applications , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[22]  Kees G. W. Goossens,et al.  Architectures and modeling of predictable memory controllers for improved system integration , 2011, 2011 Design, Automation & Test in Europe.

[23]  Edward A. Lee,et al.  PRET DRAM controller: Bank privatization for predictability and temporal isolation , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[24]  Hyojin Choi,et al.  Memory access pattern-aware DRAM performance model for multi-core systems , 2011, (IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE.

[25]  Kees G. W. Goossens,et al.  Memory-map selection for firm real-time SDRAM controllers , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[26]  Mor Harchol-Balter,et al.  Thread Cluster Memory Scheduling , 2011, IEEE Micro.

[27]  Björn Andersson,et al.  Bounding memory interference delay in COTS-based multi-core systems , 2014, 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS).

[28]  Kees G. W. Goossens,et al.  Dynamic Command Scheduling for Real-Time Memory Controllers , 2014, 2014 26th Euromicro Conference on Real-Time Systems.

[29]  Rodolfo Pellizzoni,et al.  Worst Case Analysis of DRAM Latency in Multi-requestor Systems , 2013, 2013 IEEE 34th Real-Time Systems Symposium.

[30]  Luca Benini,et al.  P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[31]  Petru Eles,et al.  Timing analysis of the FlexRay communication protocol , 2006, 18th Euromicro Conference on Real-Time Systems (ECRTS'06).

[32]  Alois Knoll,et al.  Bounding WCET of applications using SDRAM with Priority Based Budget Scheduling in MPSoCs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[33]  Rodolfo Pellizzoni,et al.  A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems , 2014, 2014 26th Euromicro Conference on Real-Time Systems.

[34]  Onur Mutlu,et al.  Self-Optimizing Memory Controllers: A Reinforcement Learning Approach , 2008, 2008 International Symposium on Computer Architecture.

[35]  Francisco J. Cazorla,et al.  Timing effects of DDR memory systems in hard real-time multicore architectures , 2013, ACM Trans. Embed. Comput. Syst..

[36]  Jörg Henkel,et al.  Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies , 2013, 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).

[37]  George A. Constantinides,et al.  Methodology for designing statically scheduled application-specific SDRAM controllers using constrained local search , 2009, 2009 International Conference on Field-Programmable Technology.

[38]  Selma Saidi,et al.  A mixed critical memory controller using bank privatization and fixed priority scheduling , 2014, 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications.

[39]  Aamer Jaleel,et al.  DRAMsim: a memory system simulator , 2005, CARN.

[40]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[41]  Kees G. W. Goossens,et al.  Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration , 2008, 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications.