An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques

This paper describes a flash ADC using interpolation (IP) and cyclic background self-calibrating techniques. The proposed IP technique that is cascade of capacitor IP and gate IP with dynamic double-tail latched comparator reduces non-linearity, power consumption, and occupied area. The cyclic background self-calibrating technique periodically suppresses offset mismatch voltages caused by static fluctuation and dynamic fluctuation due to temperature and supply voltage changes. The ADC has been fabricated in 90-nm 1P10M CMOS technology. Experimental results show that the ADC achieves SNDR of 6.07bits without calibration and 6.74bits with calibration up to 500MHz input signal at sampling rate of 600MSps. It dissipates 98.5mW on 1.2-V supply. FoM is 1.54pJ/conv.

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