Variable reduction in MOS timing models

It is shown how careful parameter reduction can be used to produce simple but very accurate macromodels for complex logic circuits. To model input and output voltage waveforms, the authors use approximations that are time-scaled and time-shifted versions of 'typical' waveforms rather than highly simplified waveforms such as ramps. To model devices, they use scaled nonlinear characteristics. Furthermore, it is shown that the technique of scaling and shifting time to obtain the response of a large class of circuits from that of a single test case applies to very complex circuit models, and can be used to handle two input parameters in a very simplified manner. Finally, to illustrate the reduced-parameter macromodeling process, the authors test a simple table-lookup CMOS delay estimation algorithm.<<ETX>>