A configurable fractionally-spaced blind adaptive equalizer for QAM demodulators

This paper discusses the design and field programmable gate array (FPGA) implementation of a configurable 18-tap fractionally-spaced blind adaptive equalizer intellectual property (IP) core for quadrature amplitude modulation (QAM) signals. The design can be configured to implement the constant modulus algorithm (CMA), multimodulus algorithm (MMA), radius-adjusted modified-multimodulus algorithm (RMMA), and radius-adjusted multimodulus decision-directed algorithm (RMDA), while it can achieve channel equalization for square QAM signals up to 256-QAM. The input samples to the equalizer tapped delay line are sampled at twice the symbol rate, while the equalizer output and tap coefficients are updated at the symbol rate. This is exploited by the equalizer tap and update modules of the design, which utilize the same hardware to implement two consecutive equalizer taps per module. The IP core is implemented for the Altera Stratix II EP2S130F780C4 FPGA and targets cable demodulators. The implementation operates at a maximum symbol frequency of 8.055 MBaud, which is comparable to recent QAM equalizer designs for cable modems.

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