Automated synthesis of cell libraries for asynchronous circuits

Asynchronous techniques are regaining relevance in the VLSI research community as they allow increasing robustness against process variability considerably, by relaxing timing assumptions. In addition, asynchronous circuits enable achieving low-power and high-speed designs. However, due to the absence of commercial dedicated standard cell libraries to take the most of asynchronous design, such circuits implementations are relegated to full-custom approaches only. This limits applicability of asynchronous solutions and avoids further development of dedicated design automation tools. This paper describes an improvement to this situation by proposing a fully-automated design-flow called ASCEnD-A, able to implement standard cells specifically required for asynchronous circuits design. The flow is capable of generating cells at the layout level, providing physical, power and timing models required by cell-based flows available in the state-of-the-art technologies.

[1]  Alex Kondratyev,et al.  Design of Asynchronous Circuits Using Synchronous CAD Tools , 2002, IEEE Des. Test Comput..

[2]  Matheus T. Moreira,et al.  NCL+: Return-to-one Null Convention Logic , 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

[3]  D. A. Edwards,et al.  The Balsa Asynchronous Circuit Synthesis System , 2000 .

[4]  Alain J. Martin,et al.  Asynchronous Techniques for System-on-Chip Design , 2006, Proceedings of the IEEE.

[5]  Matheus T. Moreira,et al.  LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries , 2013, 2013 Euromicro Conference on Digital System Design.

[6]  Peter A. Beerel,et al.  Proteus: An ASIC Flow for GHz Asynchronous Designs , 2011, IEEE Design & Test of Computers.

[7]  Laurent Fesquet,et al.  Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits , 2005, VLSI-SoC.

[8]  Luciano Lavagno,et al.  Automated synthesis of micro-pipelines from behavioral Verilog HDL , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[9]  Mayler G. A. Martins,et al.  Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? , 2014, 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems.

[10]  Ran Ginosar,et al.  An Efficient Implementation of Boolean Functions as Self-Timed Circuits , 1992, IEEE Trans. Computers.

[11]  Edith Beigné,et al.  A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits , 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.

[12]  Scott A. Brandt,et al.  NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis , 1996, Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96.

[13]  Doug A. Edwards,et al.  Teak: A Token-Flow Implementation for the Balsa Language , 2009, 2009 Ninth International Conference on Application of Concurrency to System Design.

[14]  Ross Smith,et al.  Asynchronous design using commercial HDL synthesis tools , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[15]  Steven M. Nowick,et al.  High-Performance Asynchronous Pipelines: An Overview , 2011, IEEE Design & Test of Computers.

[16]  Mohamed I. Elmasry,et al.  A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element , 1996, ISLPED.

[17]  Marly Roncken,et al.  The VLSI-programming language Tangram and its translation into handshake circuits , 1991, Proceedings of the European Conference on Design Automation..

[18]  Steven M. Nowick,et al.  Technology Mapping and Cell Merger for Asynchronous Threshold Networks , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Matheus T. Moreira,et al.  Automatic layout synthesis with ASTRAN applied to asynchronous cells , 2014, 2014 IEEE 5th Latin American Symposium on Circuits and Systems.

[20]  Steven M. Nowick,et al.  Technology Mapping and Cell Merger for Asynchronous Threshold Networks , 2008, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Matheus T. Moreira,et al.  A 65nm standard cell set and flow dedicated to automated asynchronous circuits design , 2011, 2011 IEEE International SOC Conference.

[22]  Robert Karmazin,et al.  cellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells , 2013, 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems.