Signal transition time effect on CMOS delay evaluation

Realistic modeling of gate delay is of great importance in evaluating circuit path performances. Nonzero signal rise and fall times contribute to gate propagation delays and must be considered for realistic characterization of standard cells. In this paper, we present an accurate and simple method to model output rise and fall times. We show that this can be obtained in a framework of a more general macromodel of delays, using step responses corrected for slow-input ramp duration effects. The concept of fast and slow transitions is clearly explained in terms of the drive current available in the structure. A first validation of this modeling has been obtained by comparing calculated inverter output-ramp duration to simulated ones (HSPICE level and foundry card model on 0.35-/spl mu/m and 0.25-/spl mu/m processes). Finally, both the delay and output-ramp modeling are validated by comparing inverter array calculated and simulated total delay values.

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