Schemes of clock recovery and synchronization in HDTV decoder SoC

In this paper, we present some design schemes of system clock recovery and synchronization in HDTV decoder SoC. First, a model of system clock recovery is introduced. Based on this model, an optimized hardware implementation is proposed. And then the scheme of synchronization about presentation and decoding is discussed. In the end, a solution to ensure decoding in abnormal conditions is explained.