论文信息 - Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

[1] Heike Riel,et al. Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si , 2015 .

[2] P. Hurley,et al. The Characterization and Passivation of Fixed Oxide Charges and Interface States in the $\hbox{Al}_{2}\hbox{O}_{3}/ \hbox{InGaAs}$ MOS System , 2013, IEEE Transactions on Device and Materials Reliability.

[3] Marc Meuris,et al. On the interface state density at In0.53Ga0.47As/oxide interfaces , 2009 .

[4] Niamh Waldron,et al. InGaAs Gate-All-Around Nanowire Devices on 300mm Si Substrates , 2014, IEEE Electron Device Letters.