SPARK: a high-level synthesis framework for applying parallelizing compiler transformations

This paper presents a modular and extensible high-level synthesis research system, called SPARK, that takes a behavioral description in ANSI-C as input and produces synthesizable register-transfer level VHDL. SPARK uses parallelizing compiler technology, developed previously, to enhance instruction-level parallelism and re-instruments it for high-level synthesis by incorporating ideas of mutual exclusivity of operations, resource sharing and hardware cost models. In this paper, we present the design flow through the SPARK system, a set of transformations that include speculative code motions and dynamic transformations and show how these transformations and other optimizing synthesis and compiler techniques are employed by a scheduling heuristic. Experiments are performed on two moderately complex industrial applications, namely MPEG-1 and the GIMP image processing tool. The results show that the various code transformations lead to up to 70 % improvements in performance without any increase in the overall area and critical path of the final synthesized design.

[1]  Kazutoshi Wakabayashi,et al.  Global scheduling independent of control dependencies based on condition vectors , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[2]  Nikil D. Dutt,et al.  Conditional speculation and its effects on performance and area for high-level synthesis , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[3]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[4]  Joseph A. Fisher,et al.  Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.

[5]  Alexandru Nicolau.  A development environment for scientific parallel programs , 1986 .

[6]  Forrest Brewer,et al.  A new symbolic technique for control-dependent scheduling , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Minjoong Rim,et al.  Global scheduling with code-motions for high-level synthesis applications , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Steven S. Muchnick,et al.  Advanced Compiler Design and Implementation , 1997 .

[9]  J.A.G. Jess,et al.  A reordering technique for efficient code motion , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[10]  Milind Girkar,et al.  Automatic Extraction of Functional Parallelism from Ordinary Programs , 1992, IEEE Trans. Parallel Distributed Syst..

[11]  Rajesh Gupta,et al.  Dynamic common sub-expression elimination during scheduling in high-level synthesis , 2002, 15th International Symposium on System Synthesis, 2002..

[12]  Guang R. Gao,et al.  A new framework for exhaustive and incremental data flow analysis using DJ graphs , 1996, PLDI '96.

[13]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[14]  Niraj K. Jha,et al.  Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[15]  Kemal Ebcioglu,et al.  An efficient resource-constrained global scheduling technique for superscalar and VLIW processors , 1992, MICRO 1992.

[16]  Alexandru Nicolau,et al.  Trailblazing: A Hierarchical Approach to Percolation Scheduling , 1993, 1993 International Conference on Parallel Processing - ICPP'93.