System architecture and key components of a multi-Giga-Hertz A/D converter with HBT

This paper reports the design and performance of a very fast 6-bit ADC system with GaAs HBT technology. The ADC system consists of a track/hold circuit and an ADC. The track/hold circuit employs an open-loop architecture and uses Schottky barrier diodes for a diode switch, and achieves 3 GS/s operation with better than 6-bit linearity. The 6-bit ADC employs folding/interpolation architecture to reduce hardware and power maintaining the high-speed operation, and it achieves DC linearity better than 7-bit.

[1]  Mau-Chung Frank Chang,et al.  Thermal design and simulation of bipolar integrated circuits , 1992 .

[2]  Mau-Chung Frank Chang,et al.  A 6-b, 4 GSa/s GaAs HBT ADC , 1995 .

[3]  T. Hornak,et al.  A 1GHz 6b ADC system , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  W. T. Colleran,et al.  An 8-bit, 2 gigasample per second analog to digital converter , 1995, GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995.

[5]  T. Hornak,et al.  A 1-GHz 6-bit ADC system , 1987 .

[6]  Hiroyuki Matsuura,et al.  Error correction algorithm for folding/interpolation ADC , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[7]  Asad A. Abidi,et al.  A 10-b, 75-MHz two-stage pipelined bipolar A/D converter , 1993 .

[8]  R. J. van de Plassche,et al.  An 8-b 650-MHz folding ADC , 1992 .

[9]  T. Grave,et al.  System architecture and key components for an 8 bit/1 GHz GaAs MESFET ADC , 1992, GaAs IC Symposium Technical Digest 1992.