Cheops: a reconfigurable data-flow system for video processing

The Cheops Imaging System is a compact, modular platform for acquisition, processing, and display of digital video sequences and model-based representations of moving scenes, and is intended as both a laboratory tool and a prototype architecture for future programmable video decoders. Rather than using a large number of general-purpose processors and dividing up image processing tasks spatially, Cheops abstracts out a set of basic, computationally intensive stream operations that may be performed in parallel and embodies them in specialized hardware. We review the Cheops architecture, describe the software system that has been developed to perform resource management, and present the results of some performance tests. >

[1]  V. Michael Bove,et al.  Hardware architecture for rapid generation of electro-holographic fringe patterns , 1995, Electronic Imaging.

[2]  V. Michael Bove,et al.  Real-time decoding and display of structured video , 1994, 1994 Proceedings of IEEE International Conference on Multimedia Computing and Systems.

[3]  Jean-Luc Gaudiot,et al.  Advanced Topics in Data-Flow Computing , 1991 .

[4]  S. Sakiyama,et al.  A 200 MIPS image signal multiprocessor on a single chip , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[5]  Edward A. Ashcroft,et al.  Proving Assertions about Parallel Programs , 1975, J. Comput. Syst. Sci..

[6]  Robert M. Lougheed,et al.  The cytocomputer: A practical pipelined image processor , 1980, ISCA '80.

[7]  V. Michael Bove Hardware and software implications of representing scenes as data , 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[8]  David E. Culler,et al.  Managing resources in a parallel machine , 1986 .

[9]  Jack B. Dennis,et al.  Data Flow Supercomputers , 1980, Computer.

[10]  A.H.M. van Roermund,et al.  A general-purpose programmable video signal processor , 1989 .

[11]  Jan M. Rabaey,et al.  A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths , 1992 .

[12]  Eugene B. Hogenauer,et al.  DDSP - A data flow computer for signal processing , 1982, International Conference on Parallel Processing.

[13]  P. Wambacq,et al.  A Multiprocessor System For Image Processing , 1985, Optics & Photonics.

[14]  Edward A. Lee Representing and exploiting data parallelism using multidimensional dataflow diagrams , 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[15]  Edward H. Adelson,et al.  Channel-compatible 6-MHZ HDTV distribution systems , 1988 .

[16]  David N. Chin,et al.  The Princeton Engine: a real-time video system simulator , 1988 .