An ilp based approach to reducing energy consumption in nocbased CMPS
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[1] Radu Marculescu,et al. Energy- and performance-aware mapping for regular NoC architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Mahmut T. Kandemir,et al. Compiler-directed channel allocation for saving power in on-chip networks , 2006, POPL '06.
[3] Mahmut T. Kandemir,et al. Reducing NoC energy consumption through compiler-directed channel voltage scaling , 2006, PLDI '06.
[4] Sharad Malik,et al. Orion: a power-performance simulator for interconnection networks , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..
[5] Krishnan Srinivasan,et al. Linear programming based techniques for synthesis of network-on-chip architectures , 2006, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..
[6] Monica S. Lam,et al. Maximizing Multiprocessor Performance with the SUIF Compiler , 1996, Digit. Tech. J..
[7] Chau-Wen Tseng. An optimizing Fortran D compiler for MIMD distributed-memory machines , 1993 .