Modeling the internal activity of an FPGA for conducted emission prediction purpose

End-users of integrated circuits need models to anticipate and solve conducted emission issues at board level in a short time. This is the purpose of the standard IEC62433-2 ICEM-CE. Although it proposes methods to extract circuit models from measurements, they cannot provide activity dependent models and may lead to inaccurate results for large and complex circuits. This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model adapted to large digital integrated circuits and validated on a FPGA. The method is based on a predictive approach using the estimation tools of the dynamic power and the data path delays proposed by the manufacturer of the integrated circuit.