Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors
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David Blaauw | Dennis Sylvester | Kaviraj Chopra | Rajeev R. Rao | K. Chopra | D. Blaauw | D. Sylvester
[1] P. Hazucha,et al. Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .
[2] Bharat L. Bhuva,et al. Simulation of SEU transients in CMOS ICs , 1991 .
[3] D. J. Fouts,et al. Modeling single-event effects in a complex digital device , 2003 .
[4] David Blaauw,et al. Logic SER reduction through flip flop redesign , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[5] C. Metra,et al. A model for transient fault propagation in combinatorial logic , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..
[6] S. Vangal,et al. Selective node engineering for chip-level soft error rate improvement [in CMOS] , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
[7] Robert Baumann,et al. Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.
[8] N. Seifert,et al. Robust system design with built-in soft-error resilience , 2005, Computer.
[9] Sung-Mo Kang,et al. Fast timing simulation of transient faults in digital circuits , 1994, ICCAD.
[10] K. Soumyanath,et al. Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 /spl mu/ , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).
[11] R. Baumann. Soft errors in advanced semiconductor devices-part I: the three radiation sources , 2001 .
[12] Peter Hazucha,et al. Characterization of soft errors caused by single event upsets in CMOS processes , 2004, IEEE Transactions on Dependable and Secure Computing.
[13] J. Tschanz,et al. Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation , 2003, IEEE International Electron Devices Meeting 2003.
[14] Bin Zhang,et al. FASER: fast analysis of soft error susceptibility for cell-based designs , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[15] Lorenzo Alvisi,et al. Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.
[16] Narayanan Vijaykrishnan,et al. The effect of threshold voltages on the soft error rate [memory and logic circuits] , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).
[17] G. R. Srinivasan,et al. Soft-error Monte Carlo modeling program, SEMM , 1996, IBM J. Res. Dev..
[18] Weizhong Wang. High performance radiation hardened register cell design on standard CMOS process , 2003, 2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668).
[19] S. Yang,et al. Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .
[20] Nur A. Touba,et al. Cost-effective approach for reducing soft error failure rate in logic circuits , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[21] Jindrich Zejda,et al. Analytical modeling of crosstalk noise waveforms using Weibull function , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[22] Todd M. Austin,et al. A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor , 2003, MICRO.
[23] B. Ricco,et al. Estimate of signal probability in combinational logic networks , 1989, [1989] Proceedings of the 1st European Test Conference.
[24] W. Burleson,et al. Accurate estimation of soft error rate (SER) in VLSI circuits , 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..
[25] Kartik Mohanram,et al. Cost-effective radiation hardening technique for combinational logic , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[26] Sung-Mo Kang,et al. Fast Timing Simulation Of Transient Faults In Digital Circuits , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[27] T. Monnier,et al. Flip-flop hardening for space applications , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).
[28] Sanjay J. Patel,et al. Characterizing the effects of transient faults on a high-performance processor pipeline , 2004, International Conference on Dependable Systems and Networks, 2004.
[29] Ming Zhang,et al. Logic soft errors in sub-65nm technologies design and CAD challenges , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[30] Leo B. Freeman. Critical charge calculations for a bipolar SRAM array , 1996, IBM J. Res. Dev..
[31] Sujit Dey,et al. A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits , 2004, Proceedings. 41st Design Automation Conference, 2004..
[32] Lloyd W. Massengill,et al. Impact of scaling on soft-error rates in commercial microprocessors , 2002 .
[33] Johan Karlsson,et al. On latching probability of particle induced transients in combinational networks , 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.
[34] Chandramouli V. Kashyap,et al. A delay metric for RC circuits based on the Weibull distribution , 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[35] G. C. Messenger,et al. Collection of Charge on Junction Nodes from Ion Tracks , 1982, IEEE Transactions on Nuclear Science.
[36] James F. Ziegler,et al. Terrestrial cosmic rays , 1996, IBM J. Res. Dev..
[37] ZhangMing,et al. Robust System Design with Built-In Soft-Error Resilience , 2005 .
[38] M. Baze,et al. Comparison of error rates in combinational and sequential logic , 1997 .
[39] Yehea I. Ismail,et al. Weibull-based analytical waveform model , 2003, IEEE Trans. on CAD of Integrated Circuits and Systems.
[40] Diana Marculescu,et al. MARS-C: modeling and reduction of soft errors in combinational circuits , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[41] Y. Yagil,et al. A systematic approach to SER estimation and solutions , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..
[42] M. Baze,et al. Attenuation of single event induced pulses in CMOS combinational logic , 1997 .