A 1 ms High-Speed Vision Chip with 3 D-Stacked 140 GOPS Column-Parallel PEs for Diverse Sensing Applications
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Masatoshi Ishikawa | Leo Miyashita | Hironobu Katayama | Yoshikazu Nitta | Sayaka Shida | Tomohiro Yamazaki | Masatsugu Kobayashi | Atsushi Nose | Shuji Uehara | Masaki Odahara | Kenichi Takamiya | Shizunori Matsumoto | Takashi Izawa | Yoshinori Muramatsu | Yasuaki Hisamatsu | Yoshihiro Watanabe
[1] M. Ishikawa,et al. A CMOS vision chip with SIMD processing element array for 1 ms image processing , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
[2] Junichi Akita,et al. Column-Parallel Architecture for Line-of-Sight Detection Image Sen or Based on Centroid Calculation , 2014 .
[3] Shida Sayaka,et al. A 1ms High-Speed Vision Chip with 3D-Stacked 140GOPS Column-Parallel PEs for Spatio-Temporal Image Processing , 2017 .
[4] S. Iwabuchi,et al. A Back-Illuminated High-Sensitivity Small-Pixel Color CMOS Image Sensor with Flexible Layout of Metal Wiring , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[5] Masatoshi Ishikawa,et al. 1 ms column parallel vision system and its application of high speed target tracking , 2000, Proceedings 2000 ICRA. Millennium Conference. IEEE International Conference on Robotics and Automation. Symposia Proceedings (Cat. No.00CH37065).
[6] Hiroshi Takahashi,et al. A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[7] Liyuan Liu,et al. 7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).