PDN Tool: Ananalytical Model to Calculate the Input Impedance of Chip and Silicon Interposer Power Distribution Network

This paper describes the job carried out for the developing of an analytical model that is able to calculates the input impedance of a power distribution network (PDN) by taking into account modeling of package and PCB. PDNs are usually already widely available, the work focuses on the chip and interposer PDN. The model has been used by an optimizer to determine the optimum position of the decoupling capacitors to be connected to the PDN.