A global interconnect design window for a three-dimensional system-on-a-chip

A global interconnect design window for a three-dimensional system-on-a-chip (3D-SoC) is established by evaluating the constraints of 1) wiring area, 2) clock wiring bandwidth, and 3) crosstalk noise. This window elucidates the optimum 3D-SoC global interconnect parameters for minimum pitch, minimum aspect ratio, or maximum clock frequency. In comparison to a two-dimensional system-on-a-chip (2D-SoC), the design window is greatly expanded for a 3D-SoC, thus reducing the sensitivity to interconnect parameter variations. In addition, the maximum global clock frequency is revealed to increase as S/sup 1.5/, where S is the number of strata. For example, a 3D-SoC with two strata has a maximum global clock frequency 2.8 times that of a 2D-SoC. This increase in on-chip bandwidth, however, comes at the expense of I/O density, highlighting the necessity for new high-density-I/O packaging techniques.

[1]  K. W. Lee,et al.  Three-dimensional shared memory fabricated using wafer stacking technology , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[2]  J.A. Davis,et al.  A three-dimensional stochastic wire-length distribution for variable separation of strata , 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).

[3]  James D. Meindl,et al.  Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networks , 2000 .

[4]  J.W. Joyner,et al.  A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC) , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

[5]  Payman Zarkesh-Ha,et al.  Prediction of interconnect fan-out distribution using Rent's rule , 2000, SLIP '00.

[6]  A. Lochtefeld,et al.  SOI Devices and Technology , 1999, 29th European Solid-State Device Research Conference.

[7]  P. Zarkesh-Ha,et al.  An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC) , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[8]  Kurt Keutzer,et al.  A global wiring paradigm for deep submicron design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Payman Zarkesh-Ha,et al.  Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip , 2000, IEEE Trans. Very Large Scale Integr. Syst..