High Performance and Area Efficient Flexible

This paper presents a new methodology for the syn- thesis of high performance flexible datapaths, targeting compu- tationally intensive digital signal processing kernels of embedded applications.Theproposedmethodologyisbasedonanovelcoarse- grained reconfigurable/flexible architectural template, which en- ables the combined exploitation of the horizontal and vertical par- allelism along with the operation chaining opportunities found in the application's behavioral description. Efficient synthesis tech- niques exploiting these architectural optimization concepts from a higher level of abstraction are presented and analyzed. Exten- sive experimentation showed average latency and area reductions up to 33.9% and 53.9%, respectively, and higher hardware area utilization, compared to previously published high performance coarse-grained reconfigurable datapaths.

[1]  Majid Sarrafzadeh,et al.  Instruction generation for hybrid reconfigurable systems , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[2]  Kiamal Z. Pekmestzi,et al.  Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths , 2009, Integr..

[3]  Rudy Lauwereins,et al.  Low Power Coarse-Grained Reconfigurable Instruction Set Processor , 2003, FPL.

[4]  Daniel Gajski,et al.  Utilizing horizontal and vertical parallelism with a no-instruction-set compiler for custom datapaths , 2005, 2005 International Conference on Computer Design.

[5]  Gerard J. M. Smit,et al.  A Flexible and Energy-Efficient Coarse-Grained Reconfigurable Architecture for Mobile Systems , 2003, The Journal of Supercomputing.

[6]  Giovanni De Micheli,et al.  Automatic instruction set extension and utilization for embedded processors , 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

[7]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[8]  Paolo Ienne,et al.  Improved use of the carry-save representation for the synthesis of complex arithmetic circuits , 2004, ICCAD 2004.

[9]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.

[10]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[11]  Miodrag Potkonjak,et al.  Performance optimization using template mapping for datapath-intensive high-level synthesis , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[13]  Carl Ebeling,et al.  RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.

[14]  Sharad Malik,et al.  The design of dynamically reconfigurable datapath coprocessors , 2004, TECS.

[15]  Cid C. de Souza,et al.  Efficient datapath merging for partially reconfigurable architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Rudy Lauwereins,et al.  ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix , 2003, FPL.

[17]  Taewhan Kim,et al.  Circuit optimization using carry-save-adder cells , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Daniel Gajski,et al.  Automatic architecture refinement techniques for customizing processing elements , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[19]  Peter Marwedel,et al.  Built-in chaining: introducing complex components into architectural synthesis , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

[20]  Spyros Tragoudas,et al.  A high-performance data path for synthesizing DSP kernels , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  George Theodoridis,et al.  A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools , 2007 .

[22]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[23]  Srivaths Ravi,et al.  Synthesis of custom processors based on extensible platforms , 2002, ICCAD 2002.

[24]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .