Understanding the impact of diode parameters on sneak current in 1Diode 1ReRAM crossbar architectures

This paper discusses the impact of the bidirectional diode parameters on the read failures in 1ReRAM 1Diode (1D1R) crossbar array memory architectures. Our studies show that while a diode is integral for the successful read operation, the maximum achievable crossbar memory capacity is a strong function of the reverse saturation current of the diode. An acceptable reverse saturation current target for diodes should be 0.1 A/cm2 for 10 nm × 10 nm ReRAM cell for high density memory. For multi-level-cell (MLC) operation, read failure for multiple high resistance states is limited by the reverse saturation current of diode while the line resistance of crossbar arrays plays significant role for read failure of multiple low resistance states.

[1]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[2]  Hans Kleemann,et al.  Organic Zener diodes: tunneling across the gap in organic semiconductor materials. , 2010, Nano letters.

[3]  Cheol Seong Hwang,et al.  A theoretical model for Schottky diodes for excluding the sneak current in cross bar array resistive memory , 2010, Nanotechnology.

[4]  Matthew D. Pickett,et al.  CMOS interface circuits for reading and writing memristor crossbar array , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[5]  David Kubánek Diode piecewise-linear function approximation circuit with current input and output , 2011, 2011 34th International Conference on Telecommunications and Signal Processing (TSP).

[6]  O. Richard,et al.  10×10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation , 2011, 2011 International Electron Devices Meeting.

[7]  L. Larcher,et al.  Comprehensive physical modeling of forming and switching operations in HfO2 RRAM devices , 2011, 2011 International Electron Devices Meeting.

[8]  Branden Long,et al.  Understanding the Role of Process Parameters on the Characteristics of Transition Metal Oxide RRAM/Memristor Devices , 2011 .

[9]  X. Y. Liu,et al.  Rectifying characteristics and implementation of n-Si/HfO2 based devices for 1D1R-based cross-bar memory array , 2012, 2012 IEEE Silicon Nanoelectronics Workshop (SNW).

[10]  Ru Huang,et al.  A New Dynamic Selector Based on the Bipolar RRAM for the Crossbar Array Application , 2012, IEEE Transactions on Electron Devices.

[11]  K. Gopalakrishnan,et al.  Large-scale (512kbit) integration of multilayer-ready access-devices based on mixed-ionic-electronic-conduction (MIEC) at 100% yield , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[12]  Saptarshi Mandal,et al.  Switching dynamics and charge transport studies of resistive random access memory devices , 2012 .

[13]  Songlin Feng,et al.  An 8-Mb Phase-Change Random Access Memory Chip Based on a Resistor-on-Via-Stacked-Plug Storage Cell , 2012, IEEE Electron Device Letters.

[14]  Abbas El Gamal,et al.  Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory , 2012, 2012 IEEE International Solid-State Circuits Conference.

[15]  Chilhee Chung,et al.  Comprehensive modeling of NAND flash memory reliability: Endurance and data retention , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[16]  Yibo Li,et al.  Switching Characteristics of $\hbox{Ru/HfO}_{2} \hbox{/TiO}_{2-x}\hbox{/Ru}$ RRAM Devices for Digital and Analog Nonvolatile Memory Applications , 2012, IEEE Electron Device Letters.

[17]  D. Atkinson,et al.  Multilevel 3 Bit-per-cell Magnetic Random Access Memory Concepts and Their Associated Control Circuit Architectures , 2012, IEEE Transactions on Nanotechnology.

[18]  K. Sarpatwari,et al.  Comprehensive Understanding on the Role of Tunnel Oxide Top Nitridation for the Reliability of Nanoscale Flash Memory , 2013, IEEE Electron Device Letters.