A Comprehensive LER-Aware TDDB Lifetime Model for Advanced Cu Interconnects

A time-dependent dielectric breakdown (TDDB) lifetime model predicting the impact of line-edge roughness (LER) on Cu interconnect reliability is proposed. The structure, validity, and accuracy of the model are evaluated and discussed. The model is applied to an interconnect scaling scenario that includes conventional patterning and spacer-defined patterning of nanometer-scale Cu wires. LER-aware TDDB lifetime predictions are obtained from the model, and consequent recommendations on how to improve the TDDB lifetime of future interconnects are derived.

[1]  Atsuko Yamaguchi,et al.  Evaluation of line-edge roughness in Cu/low-k interconnect patterns with CD-SEM , 2009, 2009 IEEE International Interconnect Technology Conference.

[2]  J. Noguchi,et al.  Dominant factors in TDDB degradation of Cu interconnects , 2005, IEEE Transactions on Electron Devices.

[3]  Karen Maex,et al.  Impact of line-edge roughness on resistance and capacitance of scaled interconnects , 2007 .

[4]  K. Sato,et al.  Integration and reliability of Cu-SiOC interconnect for ArF/90-nm node CMOS technology , 2004, IEEE Transactions on Electron Devices.

[5]  E. Gebreselasie,et al.  Line edge roughness and spacing effect on low-k TDDB characteristics , 2008, 2008 IEEE International Reliability Physics Symposium.

[6]  Guido Groeseneken,et al.  A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides , 1995, Proceedings of International Electron Devices Meeting.

[7]  Guido Groeseneken,et al.  A new analytic model for the description of the intrinsic oxide breakdown statistics of ultra-thin oxides , 1996 .

[8]  Atsuko Yamaguchi,et al.  Characterization of line-edge roughness in Cu/low-k interconnect pattern , 2007, SPIE Advanced Lithography.

[9]  Milton Ohring,et al.  Reliability and Failure of Electronic Materials and Devices, Second Edition , 1998 .

[10]  Linda S. Milor,et al.  A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation , 2009, Microelectron. Reliab..

[11]  G. Beyer,et al.  Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM) , 2010, 2010 IEEE International Interconnect Technology Conference.

[12]  M. Shinosky,et al.  Critical ultra low-k TDDB reliability issues for advanced CMOS technologies , 2009, 2009 IEEE International Reliability Physics Symposium.

[13]  F. Volpi,et al.  Copper line topology impact on the SiOCH low-k reliability in sub 45nm technology node. From the time-dependent dielectric breakdown to the product lifetime , 2009, 2009 IEEE International Reliability Physics Symposium.

[14]  Yunlong Li Low-k dielectric reliability in copper interconnects , 2007 .

[15]  S. Demuynck,et al.  Quantifying LER to predict its impact on BEOL TDDB reliability at 20nm ½ pitch , 2010, 2010 IEEE International Interconnect Technology Conference.

[16]  K. Takeda,et al.  Characterization of Line-Edge Roughness in Cu/Low-k Interconnect Pattern , 2008 .

[17]  Atsuko Yamaguchi,et al.  Spectral analysis of line-edge roughness in polyphenol EB-resists and its impact on transistor performance , 2005 .

[18]  Seiichi Kondo,et al.  Low-damage low-k etching with an environmentally friendly CF3I plasma , 2008 .

[19]  H. Kawada,et al.  A Discussion on How to Define the Tolerance for Line-Edge or Linewidth Roughness and Its Measurement Methodology , 2007, IEEE Transactions on Semiconductor Manufacturing.

[20]  Fen Chen,et al.  Addressing Cu/Low-$k$ Dielectric TDDB-Reliability Challenges for Advanced CMOS Technologies , 2009, IEEE Transactions on Electron Devices.

[21]  M. Stucchi,et al.  Impact of LER on BEOL dielectric reliability: A quantitative model and experimental validation , 2009, 2009 IEEE International Interconnect Technology Conference.

[22]  G. Beyer,et al.  Low-k dielectric reliability: impact of test structure choice, copper and integrated dielectric quality , 2008, 2008 International Interconnect Technology Conference.

[23]  A. Asenov,et al.  Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness , 2003 .

[24]  Seiichi Kondo,et al.  Reduction effect of line edge roughness on time-dependent dielectric breakdown lifetime of Cu/low-k interconnects by using CF3I etching , 2009 .

[25]  R. Rooyackers,et al.  Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield , 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..