Analysis of Multiprocessors with Private Cache Memories

This paper presents an approximate analytical model for the performance of multiprocessors with private cache memories and a single shared main memory. The accuracy of the model is compared with simulation results and is found to be very good over a broad range of parameters. The parameters of the model are the size of the multiprocessor, the size and type of the interconnection network, the cache miss-ratio, and the cache block transfer time. The analysis is extended to include several different read/write policies such as write-through, load-through, and buffered write-back. The analytical technique presented is also applicable to the performance of interconnection networks under block transfer mode.

[1]  Alan Jay Smith,et al.  Interference in multiprocessor computer systems with interleaved memory , 1976, CACM.

[2]  Charles E. Skinner,et al.  Effects of Storage Contention on System Performance , 1969, IBM Syst. J..

[3]  Robert M. Meade,et al.  On memory system design , 1899, AFIPS '70 (Fall).

[4]  William Daniel Strecker An analysis of the instruction execution rate in certain computer structures , 1970 .

[5]  Dileep Bhandarkar,et al.  Analysis of Memory Interference in Multiprocessors , 1975, IEEE Transactions on Computers.

[6]  William D. Strecker Cache memories for PDP-11 family computers , 1976, ISCA.

[7]  Janak H. Patel Performance of Processor-Memory Interconnections for Multiprocessors , 1981, IEEE Transactions on Computers.

[8]  Calvin K. Tang Cache system design in the tightly coupled multiprocessor system , 1976, AFIPS '76.

[9]  C. V. Ravi,et al.  On the Bandwidth and Interference in Interleaved Memory Systems , 1972, IEEE Transactions on Computers.

[10]  B. Ramakrishna Rau,et al.  Interleaved Memory Bandwidth in a Model of a Multiprocessor Computer System , 1979, IEEE Transactions on Computers.

[11]  Axel Lehmann Performance evaluation and prediction of storage hierarchies , 1980, PERFORMANCE '80.

[12]  Gururaj S. Rao,et al.  Performance Analysis of Cache Memories , 1978, JACM.

[13]  Leonard J. Shustek,et al.  An instruction timing model of CPU performance , 1977, ISCA '77.

[14]  Paul Feautrier,et al.  A New Solution to Coherence Problems in Multicache Systems , 1978, IEEE Transactions on Computers.

[15]  Robert O. Winder,et al.  Cache-based Computer Systems , 1973, Computer.