Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits

The ITRS (International Technology Roadmap forSemiconductors) predicts aggressive scaling down of devicesize, transistor threshold voltage and oxide thickness to meetgrowing demands for performance. Such scaling will resultin an exponential increase in leakage current and largevariability in threshold voltage both within and across dies.Device counts will increase from about 0.2B/chip today toapproximately 10B/chip in a decade. This 50X increase indevice count will increase not only the active powerdissipation, but also the standby or the quiescent power.Hence, designers are required to use innovative aggressivepower management strategies to meet the power constraints.The exponential increase in leakage, the device parametervariations, and aggressive power management techniques areexpected to severely impact the way integrated circuits aretested today. This paper explores test considerations for thescaled CMOS circuits in the nanometer regime.