IDDQ Testing: Issues Present and Future

I/sub DDQ/ testing has emerged from a company specific CMOS IC test technology in the 1960s and 1970s to become a worldwide accepted technique that is a requirement for low defective parts per million levels and failure rates. It is the single most sensitive test method to detect CMOS IC defects, and an abundance of studies have laid a solid foundation for why this is so. The I/sub DDQ/ test uses the quiescent power supply current of logic states as an indication of defect presence. Its major requirement for maximum efficiency is that the design implement nanowatt power levels (nanoampere supply current) in the quiescent portion of the power supply current. No direct connections are allowed between V/sub DD/ and V/sub SS/ during the quiescent period. I/sub DDQ/ testing has increased significantly since 1990, highlighting problems and driving solutions not addressed by the high reliability manufacturers of earlier technologies. Faster I/sub DDQ/ instrumentation and better software tools to generate and grade I/sub DDQ/ test patterns result from this increased interest. We address two major issues confronting I/sub DDQ/ testing: yield loss and increased background current of deep submicron IC technologies projected by the Semiconductor Industry Association/Sematech road map. Both issues are points of controversy.

[1]  Kenneth M. Wallquist.  On the effect of I/sub SSQ/ testing in reducing early failure rate , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[2]  C.F. Hawkins,et al.  Identifying defects in deep-submicron CMOS ICs , 1996, IEEE Spectrum.

[3]  D. L. Landis,et al.  Feasibility of employing an I/sub DDQ/ output amplifier in deep submicron built-in current sensors , 1996, Digest of Papers 1996 IEEE International Workshop on IDDQ Testing.

[4]  M. Ray Mercer,et al.  Iddq testing for high performance CMOS-the next ten years , 1996, Proceedings ED&TC European Design and Test Conference.

[5]  Manoj Sachdev.  SeparateIDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis , 1996, J. Electron. Test..

[6]  Charles F. Hawkins,et al.  IDDQ testing: A review , 1992, J. Electron. Test..

[7]  Víctor H. Champac,et al.  Quiescent current analysis and experimentation of defective CMOS circuits , 1992, J. Electron. Test..

[8]  Jerry M. Soden,et al.  High resolution I/sub DDQ/ characterization and testing-practical issues , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[9]  Charles F. Hawkins,et al.  Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs , 1986, ITC.

[10]  Wojciech Maly,et al.  Current signatures [VLSI circuit testing] , 1996, Proceedings of 14th VLSI Test Symposium.

[11]  Thomas M. Storey,et al.  STUCK FAULT AND CURRENT TESTING COMPARISON USING CMOS CHIP TEST , 1991, 1991, Proceedings. International Test Conference.

[12]  Wojciech Maly,et al.  Testing oriented analysis of CMOS ICs with opens , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[13]  Timothy R. Henry,et al.  Burn-in elimination of a high volume microprocessor using I/sub DDQ/ , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[14]  Chenming Hu,et al.  Hot-electron-induced MOSFET degradation—Model, monitor, and improvement , 1985, IEEE Transactions on Electron Devices.

[15]  Wojciech Maly,et al.  Design of ICs applying built-in current testing , 1992, J. Electron. Test..

[16]  F. Joel Ferguson,et al.  Sandia National Labs , 2022 .

[17]  Scott Davidson.  Is I/sub DDQ/ yield loss inevitable? , 1994, Proceedings., International Test Conference.

[18]  Robert C. Aitken,et al.  IDDQ testing as a component of a test suite: The need for several fault coverage metrics , 1992, J. Electron. Test..

[19]  J. M. Soden,et al.  Viewpoint: Dealing With Yield Losses in Iddq Testing , 1996 .