A Low-Cost Solution for Deploying Processor Cores in Harsh Environments

Nowadays, a number of processor cores are available, either as soft intellectual property (IP) cores or as hard macros that can be employed in developing new systems on a chip. Developers of applications targeting harsh environments like the atmospheric radiation environment or the space radiation environment may benefit from the computing power of processor cores, provided that suitable techniques are available for guaranteeing their correct operations in presence of the ionizing radiation that abounds in such environments. In this paper, we describe a design flow and hardware/software architecture to successfully deploy processor IP cores in harsh environments. Experimental data are provided that confirm the robustness of the presented architecture with respect to transient errors induced by radiation and suggest the possibility of employing such architectures in deep-space exploration missions.

[1]  María José Moure,et al.  Features, Design Tools, and Application Domains of FPGAs , 2007, IEEE Transactions on Industrial Electronics.

[2]  Luca Fanucci,et al.  Design and Verification of Hardware Building Blocks for High-Speed and Fault-Tolerant In-Vehicle Networks , 2011, IEEE Transactions on Industrial Electronics.

[3]  Adam Piotrowski,et al.  Compiler-level implementation of single Event Upset errors mitigation algorithms , 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.

[4]  Ricardo Reis,et al.  An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs , 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[5]  G.R. Allen Compendium of Test Results of Single Event Effects Conducted by the Jet Propulsion Laboratory , 2008, 2008 IEEE Radiation Effects Data Workshop.

[6]  Po-Lei Lee,et al.  Hardware Implementation of EMD Using DSP and FPGA for Online Signal Processing , 2011, IEEE Transactions on Industrial Electronics.

[7]  Massimo Violante,et al.  Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs , 2011, IEEE Transactions on Industrial Electronics.

[8]  Michel Pignol DMT and DT2: two fault-tolerant architectures developed by CNES for COTS-based spacecraft supercomputers , 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

[9]  Massimo Violante,et al.  Exploiting circuit emulation for fast hardness evaluation , 2001 .

[10]  Massimo Violante,et al.  Software-Implemented Hardware Fault Tolerance , 2010 .

[11]  C. Carmichael,et al.  Single Event Upsets in Xilinx Virtex-4 FPGA Devices , 2006, 2006 IEEE Radiation Effects Data Workshop.

[12]  Massimo Violante,et al.  A new software-based technique for low-cost fault-tolerant application , 2003, Annual Reliability and Maintainability Symposium, 2003..

[13]  Fabian Vargas,et al.  Hybrid soft error detection by means of infrastructure IP cores [SoC implementation] , 2004 .

[14]  S. Rezgui,et al.  New Methodologies for SET Characterization and Mitigation in Flash-Based FPGAs , 2007, IEEE Transactions on Nuclear Science.

[15]  M. Namjoo,et al.  WATCHDOG PROCESSORS AND CAPABILITY CHECKING , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

[16]  D. Merodio,et al.  Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-Based FPGAs , 2007, IEEE Transactions on Nuclear Science.

[17]  Edward J. McCluskey,et al.  Concurrent Error Detection Using Watchdog Processors - A Survey , 1988, IEEE Trans. Computers.

[18]  C. Carmichael,et al.  SEU mitigation testing of Xilinx Virtex II FPGAs , 2003, 2003 IEEE Radiation Effects Data Workshop.

[19]  Eric Monmasson,et al.  FPGA Design Methodology for Industrial Control Systems—A Review , 2007, IEEE Transactions on Industrial Electronics.

[20]  R. Velazco,et al.  Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors , 2000 .

[21]  Dhiraj K. Pradhan,et al.  Processor- and memory-based checkpoint and rollback recovery , 1993, Computer.

[22]  Ricardo Reis,et al.  A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[23]  Edward J. McCluskey,et al.  ED4I: Error Detection by Diverse Data and Duplicated Instructions , 2002, IEEE Trans. Computers.

[24]  G.M. Swift,et al.  Single Event Effects Test Results for Advanced Field Programmable Gate Arrays , 2006, 2006 IEEE Radiation Effects Data Workshop.