Bias-Stress-Induced Stretched-Exponential Time Dependence of Charge Injection and Trapping in Amorphous Silicon Thin-Film Transistors

We investigate the threshold voltage instabilities in nitride/oxide dual gate dielectric hydrogenated amorphous silicon (a-Si:H) thin-film transistors as a function of stress time, stress temperature and stress bias. The measured threshold voltage shifts are quantitatively modelled with a stretched-exponential stress time dependence where the stretched-exponent P cannot be related to the f : TsrlTo but rather to fr = TSrlTd fro for I57 ( 80'C; for I57 > 80'C the p is stress temperature independent. We have also found that p is stress gate bias independent. These findings are explained with a multiple trapping model with states located at the a-Si:H/a-SiNr:H interface and in the a-SiN*:H transitional layer close to the interface.