Formal verification of PLC programs

This paper presents an approach to the verification of programs for programmable logic controllers (PLCs) using SMV, a software package for formal verification of state transition systems. Binary PLC programs are converted directly into SMV modules that retain the variable names and execution sequences of the original programs. The system being controlled is modeled by a C/E system block diagram which is also transformed into a set of SMV modules, retaining the structure of the block diagram model. SMV allows the engineer to verify the behavior of the control program over all possible operating conditions. Mechanisms are discussed for representing correctly the concurrent execution of the PLC programs and the plant model using SMV primitives. The SMV approach to PLC program verification is illustrated with an example.

[1]  J. E. Reich,et al.  Symbolic Simulation Based Techniques for Debugging Discrete Control Programs , 1996 .

[2]  Mark N. Wegman,et al.  Efficiently computing static single assignment form and the control dependence graph , 1991, TOPL.

[3]  John B. Shoven,et al.  I , Edinburgh Medical and Surgical Journal.

[4]  Guido Wimmel.  A BDD-based Model Checker for the PEP Tool , 1997 .

[5]  H.-M. Hanisch,et al.  Net condition/event systems with multiple condition outputs , 1995, Proceedings 1995 INRIA/IEEE Symposium on Emerging Technologies and Factory Automation. ETFA'95.

[6]  H.-M. Hanisch,et al.  Modeling of PLC behavior by means of timed net condition/event systems , 1997, 1997 IEEE 6th International Conference on Emerging Technologies and Factory Automation Proceedings, EFTA '97.

[7]  Monika Heiner,et al.  VERIFICATION AND OPTIMIZATION OF CONTROL PROGRAMS BY PETRI NETS WITHOUT STATE EXPLOSION 1) , 1997 .

[8]  Kenneth L. McMillan,et al.  The SMV System , 1993 .

[9]  Gary J. Powers,et al.  Verification of a logically controlled, solids transport system using symbolic model checking , 1997 .

[10]  Edmund M. Clarke,et al.  Symbolic model checking for sequential circuit verification , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..