Wideband Continuous-Time Multi-Bit Delta-Sigma ADCs
暂无分享,去创建一个
[1] José Silva-Martínez,et al. A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback , 2010, IEEE Journal of Solid-State Circuits.
[2] Hajime Shibata,et al. A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[3] R. Schreier,et al. Delta-sigma data converters : theory, design, and simulation , 1997 .
[4] Y. Arai,et al. A CMOS time to digital converter VLSI for high-energy physics , 1988, Symposium 1988 on VLSI Circuits.
[5] T.S. Fiez,et al. A 14-bit current-mode /spl Sigma//spl Delta/ DAC based upon rotated data weighted averaging , 2000, IEEE Journal of Solid-State Circuits.
[6] C. Holuigue,et al. A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB , 2006, IEEE Journal of Solid-State Circuits.
[7] Jan Craninckx,et al. A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS , 2009, IEEE Journal of Solid-State Circuits.
[8] Krishnamurthy Soumyanath,et al. A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT ΔΣ ADC for 802.11n/WiMAX Receivers , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[9] Vijayakumar Dhanasekaran. Baseband analog circuits in deep-submicron cmos technologies targeted for mobile multimedia , 2009 .
[10] Sebastian Hoyos,et al. A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider , 2009, 2009 IEEE Custom Integrated Circuits Conference.
[11] Thomas Blon,et al. A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB , 2006 .
[12] Sebastian Hoyos,et al. A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth , 2010, IEEE Journal of Solid-State Circuits.
[13] M.Z. Straayer,et al. A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer , 2008, IEEE Journal of Solid-State Circuits.
[14] Francisco Colodro Ruiz,et al. New Continuous-Time Multibit Sigma–Delta Modulators With Low Sensitivity to Clock Jitter , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.
[15] J. Silva-Martinez,et al. Digital based calibration technique for continuous-time bandpass sigma-delta analog-to-digital converters , 2009 .
[16] Edgar Sánchez-Sinencio,et al. A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[17] Yannis P. Tsividis. Digital signal processing in continuous time: a possibility for avoiding aliasing and reducing quantization error , 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.
[18] M.Z. Straayer,et al. A 10-bit 20MHz 38mW 950MHz CT ΣΔ ADC with a 5-bit noise-shaping VCO-based quantizer and DEM circuit in 0.13u cmos , 2007, 2007 IEEE Symposium on VLSI Circuits.
[19] Holmes,et al. Pulse width modulation for power converters , 2003 .
[20] W. Martin Snelgrove,et al. Continuous-time delta-sigma modulators for high-speed a/d conversion , 2013 .
[21] Thomas H. Lee,et al. A unified model for injection-locked frequency dividers , 2003, IEEE J. Solid State Circuits.
[22] Jose Silva-Martinez,et al. A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors , 2003, IEEE J. Solid State Circuits.
[23] Michael H. Perrott,et al. A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer , 2008, VLSIC 2008.
[24] Frank Henkel,et al. Excess loop delay effects in continuous-time quadrature bandpass sigma-delta modulators , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[25] Ian Galton,et al. A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs , 2001 .
[26] Chuan Yi Tang,et al. A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..
[27] G. Temes. Delta-sigma data converters , 1994 .
[28] Thomas A. Lipo,et al. Pulse Width Modulation for Power Converters: Principles and Practice , 2003 .
[29] Robert H. M. van Veldhoven,et al. A 56 mW Continuous-Time Quadrature Cascaded $\Sigma\Delta$ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band , 2007, IEEE Journal of Solid-State Circuits.