Gate induced drain leakage reduction with analysis of gate fringing field effect on high-κ/metal gate CMOS technology

We suggest the optimum permittivity for a high-κ/metal gate (HKMG) CMOS structure based on the trade-off characteristics between the fringing field induced barrier lowering (FIBL) and gate induced drain leakage (GIDL). By adopting the high-κ gate dielectric, the GIDL from the band-to-band tunneling at the interface of gate and lightly doped drain (LDD) is suppressed with wide tunneling width owing to the enhanced fringing field, while the FIBL effects is degenerated as the previous reports. These two effects from the gate fringing field are studied extensively to manage the leakage current of HKMG for low power applications.

[1]  E. Cartier,et al.  Ultrathin high-K metal oxides on silicon: processing, characterization and integration issues , 2001 .

[2]  D. Muller,et al.  The electronic structure at the atomic scale of ultrathin gate oxides , 1999, Nature.

[3]  Low Gate-Induced Drain Leakage and Its Physical Origins in Si Nanowire Transistors , 2011 .

[4]  Jeffrey Bokor,et al.  Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs , 2003 .

[5]  Jianjun Jiang,et al.  Fringe-induced barrier lowering (FIBL) included sub-threshold swing model for double-gate MOSFETs , 2008 .

[6]  C. Hu,et al.  Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model , 1992 .

[7]  Karen Willcox,et al.  Kinetics and kinematics for translational motions in microgravity during parabolic flight. , 2009, Aviation, space, and environmental medicine.

[8]  Hot carrier effect on gate-induced drain leakage current in high-k/metal gate n-channel metal-oxide-semiconductor field-effect transistors , 2011 .

[9]  Jong-Ho Lee,et al.  Gate-Induced Drain Leakage Currents in Metal Oxide Semiconductor Field Effect Transistors with High-κ Dielectric , 2002 .

[10]  M. Shur,et al.  Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs , 1993 .

[11]  Li Qiang Zhu,et al.  integrations and challenges of novel high-k gate stacks in advanced cmos technology , 2011 .

[12]  Y. Taur,et al.  Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's , 1997, IEEE Electron Device Letters.

[13]  Yuan Taur,et al.  A 2D analytical model for SCEs in MOSFETs with high-k gate dielectric , 2010 .

[14]  T.Y. Chan,et al.  The impact of gate-induced drain leakage current on MOSFET scaling , 1987, 1987 International Electron Devices Meeting.

[15]  S. Ikegawa,et al.  Electrical Properties of Single Crystalline CeO2 High-k Gate Dielectrics Directly Grown on Si (111) , 2002 .

[16]  J. Autran,et al.  Performance degradation induced by fringing field-induced barrier lowering and parasitic charge in double-gate metal-oxide-semiconductor field-effect transistors with high-kappa dielectrics , 2005 .

[17]  D. Frank,et al.  Generalized scale length for two-dimensional effects in MOSFETs , 1998, IEEE Electron Device Letters.

[18]  Bing-Yue Tsui,et al.  A comprehensive study on the FIBL of nanoscale MOSFETs , 2004 .

[19]  K. Kao,et al.  Fringing Electric Field Effect on 65-nm-Node Fully Depleted Silicon-on-Insulator Devices , 2006 .

[20]  T. Tanaka,et al.  Gate-fringing field effects on high performance in high dielectric LDD spacer MOSFETs , 1992 .

[22]  Madhav P. Desai,et al.  Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[23]  Recessed Channel Fin Field-Effect Transistor Cell Technology for Future-Generation Dynamic Random Access Memories , 2008 .

[24]  C. Mazure,et al.  Impact of LDD spacer reduction on MOSFET performance for sub- mu m gate/space pitches , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[25]  Ming-Ren Lin,et al.  Fringing-induced barrier lowering (FIBL) in sub-100 nm MOSFETs with high-K gate dielectrics , 1998 .

[26]  J.M.C. Stork,et al.  The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs , 1999 .

[27]  Z. Weinberg,et al.  On tunneling in metal‐oxide‐silicon structures , 1982 .

[28]  Qiang Chen,et al.  Fringe-induced barrier lowering (FIBL) included threshold voltage model for double-gate MOSFETs , 2005 .

[29]  B. Ghosh,et al.  Dynamic threshold voltage operation in Si and SiGe source junctionless tunnel field effect transistor , 2014 .