High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation

This study developed a high accuracy dynamic error-compensation circuit for fixed-width Booth multipliers based on probability and computer simulation (PACS). PACS begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed PACS approach is area-effective. This study used the TSMC 0.18-μm CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.

[1]  Vojin G. Oklobdzija,et al.  Evaluation of Booth encoding techniques for parallel multiplier implementation , 1993 .

[2]  A. Inoue,et al.  A 4.1 ns compact 54/spl times/54 b multiplier utilizing sign select Booth encoders , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[3]  I-Chyn Wey,et al.  Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Keshab K. Parhi,et al.  Low error fixed-width CSD multiplier with efficient sign extension , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[5]  Vojin G. Oklobdzija,et al.  A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach , 1996, IEEE Trans. Computers.

[6]  Shyh-Jye Jou,et al.  Low-error reduced-width Booth multipliers for DSP applications , 2003 .

[7]  Chip-Hong Chang,et al.  Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  In-Cheol Park,et al.  Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Shiann-Rong Kuang,et al.  High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Yuan-Ho Chen,et al.  A statistical error-compensated Booth multipliers and its DCT applications , 2010, TENCON 2010 - 2010 IEEE Region 10 Conference.

[11]  Shiann-Rong Kuang,et al.  Modified Booth Multipliers With a Regular Partial Product Array , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  Tsin-Yuan Chang,et al.  Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[13]  Ch. Nirmala,et al.  STBC-OFDM DOWNLINK BASEBAND RECEIVER FOR MOBILE WMAN , 2014 .

[14]  Lan-Da Van,et al.  Design of the lower error fixed-width multiplier and its application , 2000 .

[15]  Tsin-Yuan Chang,et al.  A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Davide De Caro,et al.  Dual-tree error compensation for high performance fixed-width multipliers , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[17]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[18]  Shih-Chang Hsia,et al.  Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Shyh-Jye Jou,et al.  A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications , 2012, IEEE Journal of Solid-State Circuits.

[20]  Sy-Yen Kuo,et al.  Adaptive Low-Error Fixed-Width Booth Multipliers , 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[21]  Shen-Fu Hsiao,et al.  Low-error carry-free fixed-width multipliers with low-cost compensation circuits , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[22]  Tsin-Yuan Chang,et al.  A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[23]  Yuan-Ho Chen.  An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.