Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array
暂无分享,去创建一个
Claudio Mucci | Fabio Campi | Luca Ciccarelli | Luca Vanzolini | Antonio Deledda | Axel Schneider | Joachim Knäblein | Sebastian Goller | Ilario Mirimin | Daniele Gazzola
[1] Subhadeep Roy. A sub-word-parallel Galois field multiply-accumulate unit for digital signal processors , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[2] Jeff H. Derby,et al. High-speed CRC computation using state-space transformations , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).
[3] Ming-Der Shieh,et al. High-speed CRC design for 10 Gbps applications , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[4] Charles A. Zukowski,et al. High-speed parallel CRC circuits in VLSI , 1992, IEEE Trans. Commun..
[5] Jürgen Becker,et al. Reconfigurable processor architectures for mobile phones , 2003, Proceedings International Parallel and Distributed Processing Symposium.
[6] Riccardo Sisto,et al. Parallel CRC generation , 1990, IEEE Micro.
[7] C. Kennedy,et al. High-speed parallel CRC circuits , 2008, 2008 42nd Asilomar Conference on Signals, Systems and Computers.
[8] Fadi J. Kurdahi,et al. MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.
[9] Keshab K. Parhi,et al. Interleaved cyclic redundancy check (CRC) code , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.
[10] H. Michael Ji,et al. Fast parallel CRC algorithm and implementation on a configurable processor , 2002, 2002 IEEE International Conference on Communications. Conference Proceedings. ICC 2002 (Cat. No.02CH37333).
[11] Seth Copen Goldstein,et al. A High-Performance Flexible Architecture for Cryptography , 1999, CHES.