Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple

On-chip voltage regulation using distributed Digital Low Drop Out (LDO) voltage regulators has been identified as a promising technique for efficient power-management for emerging multi-core processors. Digital LDOs (DLDO) can offer low voltage operation, faster transient response, and higher current efficiency. Response time as well as output voltage ripple can be reduced by increasing the speed of the dynamic comparators. However, the comparator offset steeply increases for high clock frequencies, thereby leading to enhanced variations in output voltage. In this work we explore the design of digital LDOs with multiple dynamic comparators that can overcome this bottleneck. In the proposed topology, we apply time-interleaved comparators with the same voltage threshold and uniform current step in order to accomplish the aforementioned features. For a load step of 50mA, a DLDO with 8 time-interleaved comparators could achieve an output ripple of less than 5mV, while achieving a settling time of less than 0.5us. Load current dependant dynamic adjustment of clock frequency is proposed to maintain high current efficiency of ~97%.

[1]  Kazunori Watanabe,et al.  0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS , 2010, IEEE Custom Integrated Circuits Conference 2010.

[2]  K. Shakeri,et al.  Compact physical IR-drop models for chip/package co-design of gigascale integration (GSI) , 2005, IEEE Transactions on Electron Devices.

[3]  Rajendran Panda,et al.  Current signature compression for IR-drop analysis , 2000, Proceedings 37th Design Automation Conference.

[4]  Peng Li,et al.  An ultra-low voltage digitally controlled low-dropout regulator with digital background calibration , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[5]  Kevin G. Stawiasz,et al.  5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[6]  Sanu Mathew,et al.  A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[7]  Sheldon X.-D. Tan,et al.  Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings , 1999, DAC '99.

[8]  James D. Meindl,et al.  A compact model for projections of future power supply distribution network requirements , 2002, 15th Annual IEEE International ASIC/SOC Conference.

[9]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[10]  T. Karnik,et al.  Area-efficient linear regulator with ultra-fast load regulation , 2005, IEEE Journal of Solid-State Circuits.

[11]  Kaushik Roy,et al.  Ultra low energy analog image processing using spin based neurons , 2012, 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

[12]  W. T. Lynch,et al.  Scaling and performance implications for power supply and other signal routing constraints imposed by I/O pad limitations , 1998, Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211).

[13]  Rajendran Panda,et al.  Design and analysis of power distribution networks in PowerPC microprocessors , 1998, DAC.

[14]  Wei Hwang,et al.  All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Kazumasa Yanagisawa,et al.  An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor , 2012, 2012 IEEE International SOC Conference.

[16]  D. Schmitt-Landsiedel,et al.  A fully-integrated system power aware LDO for energy harvesting applications , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[17]  Sundari Mitra,et al.  Design of an efficient power distribution network for the UltraSPARC-I microprocessor , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[18]  S. Rajapandian,et al.  High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters , 2007, IEEE Journal of Solid-State Circuits.

[19]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[20]  Larry L. Biro,et al.  Power considerations in the design of the Alpha 21264 microprocessor , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[21]  Torsten Werner,et al.  Fundamentals Of Microsystems Packaging , 2016 .

[22]  Ernest S. Kuh,et al.  Power and ground network topology optimization for cell based VLSIs , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.