Stochastic Processors on FPGAs to Compute Sensor Data Towards Fault-Tolerant IoT Systems

The continuous increase in the amounts of data received at the edges of the Grid is pushing the pre-computation of sensor data at the IoT device before communicating it over the network. Moreover, in the IoT context, devices are often required to operate under heavy power and area constraints and be subjected to harsh environments. However, in this context, traditional computing paradigms struggle to provide high availability and fault-tolerance. Stochastic Computing has emerged as a competitive computing paradigm that produces fast and compact implementations of arithmetic operations, while offering high levels of parallelism, and graceful degradation when in the presence of faults. Stochastic Computing is based on the computation of pseudo-random sequences of bits, hence requiring only a single bitstream per signal. In virtue of the granularity of the bitstreams, the bit-level specification of circuits, high-performance characteristics and reconfigurable capabilities, FPGAs are often adopted to implement and test such systems. This work presents a tool that takes a high-level specification and automatically creates a complete Stochastic Computing systems capable of interfacing analog sensors directly on the FPGA, and perform computations over the stochastic bitstreams. Moreover, the presented framework is also able to generate custom stochastic processing units, perform fault-tolerance tests, and report estimates on performance, resources and power. As a proof-of-concept, this paper presents two Machine Learning applications typical in the IoT context, implementing Karhunen-Loeve Transform for data compression and Neural Networks for classification.

[1]  Kia Bazargan,et al.  IIR filters using stochastic arithmetic , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  Brian R. Gaines,et al.  Stochastic Computing Systems , 1969 .

[3]  Keshab K. Parhi,et al.  Architectures for digital filters using stochastic computing , 2013, 2013 IEEE International Conference on Acoustics, Speech and Signal Processing.

[4]  C G Drury,et al.  Electronic calculators: which notation is the better? , 1980, Applied ergonomics.

[5]  Xin Li,et al.  An Architecture for Fault-Tolerant Computation with Stochastic Logic , 2011, IEEE Transactions on Computers.

[6]  John P. Hayes,et al.  Survey of Stochastic Computing , 2013, TECS.

[7]  Colin G. Drury,et al.  Human behaviour and performance in calculator use with Algebraic and Reverse Polish Notation , 1979 .

[8]  Xilinx Family Efficient Shift Registers, LFSR Counters, and Long Pseudo- Random Sequence Generators , 1996 .

[9]  Fan Zhou,et al.  Field-programmable gate array implementation of a probabilistic neural network for motor cortical decoding in rats , 2010, Journal of Neuroscience Methods.

[10]  Dharmendra S. Modha,et al.  A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[11]  Mário P. Véstias,et al.  XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system , 2016, 2016 IEEE International Conference on Rebooting Computing (ICRC).

[12]  Alain J. Martin,et al.  Asynchronous Techniques for System-on-Chip Design , 2006, Proceedings of the IEEE.

[13]  B. Gaines Techniques of Identification with the Stochastic Computer , 1967 .

[14]  Howard C. Card,et al.  Stochastic Neural Computation I: Computational Elements , 2001, IEEE Trans. Computers.

[15]  John Shawe-Taylor,et al.  Stochastic bit-stream neural networks , 1999 .

[16]  Mário P. Véstias,et al.  Enhancing stochastic computations via process variation , 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

[17]  B. DeSalvo,et al.  CBRAM devices as binary synapses for low-power stochastic neuromorphic systems: Auditory (Cochlea) and visual (Retina) cognitive processing applications , 2012, 2012 International Electron Devices Meeting.

[18]  J. von Neumann,et al.  Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[19]  John Wawrzynek,et al.  High-throughput bayesian computing machine with reconfigurable hardware , 2010, FPGA '10.

[20]  J. Dias,et al.  Synthesis of Bayesian Machines On FPGAs Using Stochastic Arithmetic , 2014 .

[21]  Christos-Savvas Bouganis,et al.  A Unified Framework for Over-Clocking Linear Projections on FPGAs under PVT Variation , 2014, ARC.

[22]  Nadia Nedjah,et al.  Reconfigurable hardware for neural networks: binary versus stochastic , 2007, Neural Computing and Applications.