FIR Filter Realization via Deferred End-Around Carry Modular Addition

Hardware realization of FIR filters that are based on residue number systems leads to increased speed and reduced power, where besides the popular Mersenne numbers, several moduli of the form <inline-formula> <tex-math notation="LaTeX">${2}^{n} \pm \delta (\delta \ge 3)$ </tex-math></inline-formula> are commonly used. However, additional weighted <inline-formula> <tex-math notation="LaTeX">${2}^{i}(i>1)$ </tex-math></inline-formula> end-around carries (EACs) slow down and complicate the required modular adders in comparison to modulo-(<inline-formula> <tex-math notation="LaTeX">${2}^{n}-1$ </tex-math></inline-formula>) adders. For example, for <inline-formula> <tex-math notation="LaTeX">$\delta =3$ </tex-math></inline-formula>, the modular sum is obtained via <inline-formula> <tex-math notation="LaTeX">$A+B\mp 3{c}_{\mathrm {out}}$ </tex-math></inline-formula>, where <inline-formula> <tex-math notation="LaTeX">${A}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${B}$ </tex-math></inline-formula> are modulo-(<inline-formula> <tex-math notation="LaTeX">${2}^{n}\pm 3$ </tex-math></inline-formula>) operands and <inline-formula> <tex-math notation="LaTeX">${c}_{\mathrm {out}}$ </tex-math></inline-formula> is the carryout of binary addition <inline-formula> <tex-math notation="LaTeX">$A+B$ </tex-math></inline-formula>. In this paper, a new multioperand modular adder is proposed, where the key improvement is that all the required EAC additions (e.g., <inline-formula> <tex-math notation="LaTeX">$+ 3c_{\mathrm {out}}$ </tex-math></inline-formula>) are postponed until after the last filter tap, whereby tens of addition operations take place without the EAC secondary addition; hence considerable savings of time, area consumption, and power dissipation. The proposed deferred EAC addition scheme has been applied to three previous relevant works. The corresponding synthesis results showed over 11%–32%, 27%–29%, and 21%–37%, reductions in delay, area, and power measures, respectively. This is achieved despite area and power overhead of the few appended stages into the pipelined architecture of the filter, which are nevertheless shown to become less significant as the number of filter taps grows.

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