Seed selection procedure for LFSR-based BIST with multiple scan chains and phase shifters
暂无分享,去创建一个
[1] G. Kiefer. Deterministic BIST with Scan Chains , 1998 .
[2] Gundolf Kiefer,et al. Application of Deterministic Logic BIST on Industrial Circuits , 2001, J. Electron. Test..
[3] S. Fukumoto,et al. A seed selection procedure for LFSR-based random pattern generators , 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..
[4] Bernard Courtois,et al. Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers , 1992 .
[5] Nur A. Touba,et al. Altering a pseudo-random bit sequence for scan-based BIST , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[6] Melvin A. Breuer,et al. Test embedding with discrete logarithms , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Nur A. Touba,et al. Reducing test data volume using external/LBIST hybrid test patterns , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[8] Tony Ambler,et al. Economics of Built-in Self-Test , 2001, IEEE Des. Test Comput..
[9] Janusz Rajski,et al. Automated synthesis of phase shifters for built-in self-testapplications , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] H. Wunderlich,et al. Bit-flipping BIST , 1996, ICCAD 1996.
[11] Masayuki Arai,et al. A seed selection procedure for LFSR-based random pattern generators , 2003, ASP-DAC '03.
[12] Gundolf Kiefer,et al. Deterministic BIST with multiple scan chains , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[13] Alex Orailoglu,et al. An examination of PRPG selection approaches for large, industrial designs , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).