On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit

The need for efficient and accurate detection schemes to mitigate the impact of process variations on the parametric yield of integrated circuits has increased in the nm design era. In this paper, a new variation detection technique is presented that uses slew as a metric along with delay to determine the mismatch between the drive strengths of NMOS and PMOS devices. The importance of considering both of these metrics is illustrated and a new slew-rate monitoring circuit is presented for measuring slew of a signal from the critical path of a circuit. Design considerations, simulation results and characteristics of the slew-rate monitor circuitry in a 45 nm SOI technology are presented, and a sensitivity of 1 MHz/ps is achieved. This scheme can detect the threshold voltage variation in the order of mV, with a sensitivity of 0.95 MHz/mV.

[1]  Vivek De,et al.  Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[2]  Kevin J. Nowka,et al.  Parametric yield analysis and constrained-based supply voltage optimization , 2005, Sixth international symposium on quality electronic design (isqed'05).

[3]  Dong-Wook Kim,et al.  A simple CMOS delay model for wide applications , 1996, Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems.

[4]  Eric S. Fetzer.  Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design , 2006, IEEE Design & Test of Computers.

[5]  Bo Zhou,et al.  Measurement of delay mismatch due to process variations by means of modified ring oscillators , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[6]  Sangbeom Park,et al.  Low-power transistor-string and new rail-to-rail comparator in A/D converter , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).

[7]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[8]  Spiridon Nikolaidis,et al.  Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices , 1998, IEEE J. Solid State Circuits.

[9]  Anas A. Hamoui,et al.  An analytical model for current, delay, and power analysis of submicron CMOS logic circuits , 2000 .

[10]  K. Takeda,et al.  Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes , 2006, IEEE Journal of Solid-State Circuits.

[11]  Alessandro Bogliolo,et al.  Measuring the effects of process variations on circuit performance by means of digitally-controllable ring oscillators , 2003, International Conference on Microelectronic Test Structures, 2003..