Semiconductor memory device and method for manufacturing the same

PURPOSE: To realize a DRAM having a memory cell size 4F2 or smaller. CONSTITUTION: The semiconductor memory device comprises a plurality of silicon posts specified by a groove formed in a lattice state on a surface of a silicon substrate, selective transistors formed on a side face of each of the posts and having source or drain diffused layers of the transistors formed in the bottom of the groove. In this case, the transistor is formed as a selective transistor of one transistor and single capacitor type DRAM memory cell. The source and drain diffused layers of the selective transistor of the bottom of the groove are connected to a predetermined common voltage of many memory cells or commonly connected at adjacent memory cells to each other, and the diffused layer is drawn via wirings on the upper part of the silicon substrate and connected to bit lines.