Optimal global interconnecting devices for GSI

Size of global interconnects is optimized to have a large bisectional bandwidth as well as small latency. Using physical models it is shown that by maximizing the bandwidth-reciprocal latency product, the delay variation due to different switching patterns decreases to less than 3%. The required silicon area for global repeaters is also less than 1% of the chip area. Compact physical models are derived for far inductive noise, which show that noise remains small and constant (less than 0.2 V/sub dd/) for all technology generations if optimal wire width is used.