A New Test Vector Search Algorithm for a Single Stuck-at Fault Using Probabilistic Correlation

It has been mathematically shown that the testing problem is NP complete. Numerous attempts have been made in creating and designing algorithms to successfully test a digital circuit for all faults in computational linear time. However, due to the complexity of the NP problem, all these attempts start becoming exponential with an increase in circuit size and complexity. Algorithms have been proposed where successful vectors have been used to search for more test vectors with similar properties. However, this leads to a bottleneck when trying to find hard to find stuck-at faults which have only one or two unique tests and their properties may not match other previously successful tests. We propose a new probability based algorithm where new test vectors are generated based on the input probability correlation of previously unsuccessful test vectors. By looking at the correlation between the primary inputs for previously generated test vectors, we use the probability information of 1's or 0's at a primary input with respect to other inputs to skew the search in the test vector space. We have shown test time improvements for a 10 input AND gate, c17 and c432 benchmark circuits. We have also shown improvements when comparing our algorithm with a random test generator and weighted-random test generator.

[1]  V. Agrawal,et al.  Spectral RTL Test Generation for Gate-Level Stuck-at Faults , 2006, 2006 15th Asian Test Symposium.

[2]  Yashwant K. Malaiya,et al.  Antirandom testing: getting the most out of black-box testing , 1995, Proceedings of Sixth International Symposium on Software Reliability Engineering. ISSRE'95.

[3]  David M. Blei,et al.  Probabilistic topic models , 2012, Commun. ACM.

[4]  Peter W. Shor,et al.  Polynomial-Time Algorithms for Prime Factorization and Discrete Logarithms on a Quantum Computer , 1995, SIAM Rev..

[5]  J. Paul Roth,et al.  Diagnosis of automata failures: a calculus and a method , 1966 .

[6]  Sheldon B. Akers,et al.  Universal Test Sets for Logic Networks , 1972, IEEE Transactions on Computers.

[7]  Vishwani D. Agrawal,et al.  A transitive closure algorithm for test generation , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Vishwani D. Agrawal,et al.  An Information Theoretic Approach to Digital Fault Testing , 1981, IEEE Transactions on Computers.

[9]  Eric Lindbloom,et al.  The Weighted Random Test-Pattern Generator , 1975, IEEE Transactions on Computers.

[10]  Sudhakar M. Reddy,et al.  Complete Test Sets for Logic Functions , 1973, IEEE Transactions on Computers.

[11]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Gadiel Seroussi,et al.  Vector sets for exhaustive testing of logic circuits , 1988, IEEE Trans. Inf. Theory.

[13]  Kurt Antreich,et al.  A formal non-heuristic ATPG approach , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[14]  Lov K. Grover A fast quantum mechanical algorithm for database search , 1996, STOC '96.

[15]  Hideo Fujiwara,et al.  The Complexity of Fault Detection Problems for Combinational Logic Circuits , 1982, IEEE Transactions on Computers.

[16]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[17]  Leslie G. Valiant,et al.  Fast probabilistic algorithms for hamiltonian circuits and matchings , 1977, STOC '77.

[18]  Oscar H. Ibarra,et al.  Polynomially Complete Fault Detection Problems , 1975, IEEE Transactions on Computers.

[19]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.