Using BIST circuitry to measure DRV of large SRAM arrays

This paper presents a new technique to measure the data retention voltage (DRV) of large SRAM arrays in the presence of process variations. The main aim of the proposed technique is to ensure that the SRAM array operates at the minimum energy point. In the proposed procedure, the DRV is measured by implementing a small test circuit on-chip consisting of a modified form of the memory Built-In Self Test (BIST) unit, a DC-DC converter and a Test Control Unit (TCU). The circuit was developed in 90nm technology and simulated using HSPICE. Previously proposed statistical techniques determine the DRV at around 150mV, whereas the proposed technique showed that the SRAM array under test could retain its data at voltages as low as 80mV which would result in significant power savings.

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