Capacity planning for semiconductor wafer fabrication with time constraints between operations

Planning capacity for wafer fabrication is complicated by time constraints between process steps. For example, if certain baking operations are not started within two hours of a prior cleaning then the lot in question must be sent back to be cleaned again. For two-element systems, an approximation based on M/M/c queuing formulas is developed and compared with results from discrete event simulations. The approximation performs well in predicting the probability of reprocessing and provides a bound that can easily be included in the spreadsheet capacity models which are often employed by manufacturers. For multi-element systems, the results of a fluid model used to understand general system characteristics are summarized. Discrete event simulation was used to validate the results of the analytic models and to provide guidelines for operating time-constrained systems.

[1]  Steven Brown,et al.  Effective implementation of cycle time reduction strategies for semiconductor back-end manufacturing , 1998, 1998 Winter Simulation Conference. Proceedings (Cat. No.98CH36274).

[2]  S. S. Johal.  Non-linearity and randomness in a semiconductor wafer fab , 1996, IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings.

[3]  Hong Chen,et al.  Empirical Evaluation of a Queueing Network Model for Semiconductor Wafer Fabrication , 1988, Oper. Res..

[4]  K. Srinivasan,et al.  Correlation between yield and waiting time: a quantitative study , 1995, Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'.

[5]  Lee W. Schruben.  Graphical Simulation Modeling and Analysis: Using Sigma for Windows (The Scientific Press Series) , 1995 .

[6]  Vijay Mehrotra,et al.  Successful modeling of a semiconductor R&D facility , 1990, IEEE/SEMI International Symposium on Semiconductor Manufacturing Science.

[7]  D. Meyersdorf,et al.  A STRATEGIC DOMAIN : IE IN THE SEMICONDUCTOR INDUSTRY , 1998 .

[8]  David D. Yao,et al.  A queueing network model for semiconductor manufacturing , 1996 .

[9]  Reha Uzsoy,et al.  A REVIEW OF PRODUCTION PLANNING AND SCHEDULING MODELS IN THE SEMICONDUCTOR INDUSTRY PART I: SYSTEM CHARACTERISTICS, PERFORMANCE EVALUATION AND PRODUCTION PLANNING , 1992 .

[10]  K. Potti,et al.  Using simulation to improve semiconductor manufacturing , 1997 .

[11]  Steven Brown.  A Centralized Approach to Factory Simulation , 1997 .

[12]  E. Reich.  Waiting Times When Queues are in Tandem , 1957 .

[13]  Carl M. Harris,et al.  Fundamentals of queueing theory (2nd ed.). , 1985 .

[14]  W. Whitt,et al.  Performance of the Queueing Network Analyzer , 1983, The Bell System Technical Journal.

[15]  A. Spence,et al.  Capacity planning of a photolithography work cell in a wafer manufacturing line , 1987, Proceedings. 1987 IEEE International Conference on Robotics and Automation.

[16]  David Y. Burman,et al.  Performance analysis techniques for IC manufacturing lines , 1986, AT&T Technical Journal.

[17]  Navdeep S. Grewal,et al.  Integrating targeted cycle-time reduction into the capital planning process , 1998, 1998 Winter Simulation Conference. Proceedings (Cat. No.98CH36274).

[18]  Jennifer K Robinson,et al.  Capacity planning in a semiconductor wafer fabrication facility with time constraints between process steps , 1998 .

[19]  Pravin K. Johri,et al.  Practical issues in scheduling and dispatching in semiconductor wafer fabrication , 1993 .