An 80mW 40Gb/s 7-Tap T/2-Spaced FFE in 65nm CMOS

The ever-increasing demand for higher communication bandwidth is pressuring the industry to produce links with 40Gb/s data rate. At this data rate, channel dispersion greatly limits the transmission length, making deployment of dispersion compensators a necessity. Due to its fast adaptation speed and ease of integration within the transceiver, electronic dispersion compensation (EDC) is receiving a great deal of attention. An FFE is currently the most practical implementation of EDC for 40Gb/s data rates, reflecting its advantages as a simple structure with moderate design complexity. Based on system-level simulations of a 40Gb/s SMF link and a T/2-spaced FFE [1], a 7-tap T/2-spaced FFE is implemented in this work.

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