Effective capacitance for gate delay with RC loads

In deep submicron designs, the resistance of interconnect plays a dominant role on the timing behavior of logic gates. The concept of effective capacitance C/sub eff/ is usually used to calculate the gate delay for interconnect loads. In this paper, a new method to derive the expression C/sub eff/ is presented, and the accuracy of the expression is discussed. In our approach, the output waveform is assumed as linear. Thus, the expression of effective capacitance is simple and efficient. Moreover, the result of effective capacitance is insensitive to output wave shape because C/sub eff/ is determined by the curve area. Therefore, it is appropriate for various output waveforms of a CMOS gate with RC loads. Experimental results show it is in agreement with the Spice simulation.

[1]  R. Macys,et al.  A new algorithm for computing the "effective capacitance" in deep sub-micron circuits , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[2]  Nicholas C. Rumin,et al.  Delay and current estimation in a CMOS inverter with an RC load , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Lawrence T. Pileggi,et al.  A Gate-Delay Model for High-Speed CMOS Circuits , 1994, 31st Design Automation Conference.

[4]  Lawrence T. Pileggi,et al.  Performance computation for precharacterized CMOS gates with RC loads , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  P.R. O'Brien,et al.  Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[6]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[7]  Massoud Pedram,et al.  Calculating the effective capacitance for the RC interconnect in VDSM technologies , 2003, ASP-DAC '03.

[8]  David Blaauw,et al.  Accurate crosstalk noise modeling for early signal integrity analysis , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Andrew B. Kahng,et al.  Improved effective capacitance computations for use in logic and layout optimization , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[10]  C. L. Ratzlaff,et al.  Modeling The RC-interconnect Effects In A Hierarchical Timing Analyzer , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[11]  Lawrence T. Pileggi,et al.  Modeling the "Effective capacitance" for the RC interconnect of CMOS gates , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..