Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression

Static noise margin is one of the key metrics to estimate the likelihood of failure of a 6T-static random-access memory (SRAM) cell. This paper proposes a technique to accurately estimate the stability of a conventional SRAM cell without modifying the cell structure. The main idea is to measure the specific cell's currents with variant supply levels via the bit lines. The measured currents are used to estimate the read stability and the write ability through a nonlinear regression. The R2 (coefficient of determination) of the stability estimation is as high as 0.95 when applied to an arbitrary data set. As typical stability definitions require an access to the internal node of a 6T-SRAM cell, alternative measurable stability metrics for read and write are surveyed and modified to improve the correlation with the conventional stability definition. With this alternative stability and the cell currents, the conversion rules from currents to the stability can be found from the measurement data. Simulation results show that the estimation error sigma is as small as 2.44% and 3% for the read stability and write-ability estimation, respectively. Validity of the idea is verified by Monte Carlo simulations by using SRAM models in a 45-nm CMOS technology.

[1]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[2]  Sani R. Nassif,et al.  The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  W. Dehaene,et al.  Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies , 2006, IEEE Journal of Solid-State Circuits.

[4]  Jian Wang,et al.  SRAM parametric failure analysis , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[5]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[6]  Yehea I. Ismail,et al.  Accurate Estimation of SRAM Dynamic Stability , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[8]  Borivoje Nikolic,et al.  Large-Scale SRAM Variability Characterization in 45 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[9]  J. Lohstroh Static and dynamic noise margins of logic circuits , 1979 .

[10]  Vivek De,et al.  Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[11]  Zheng Guo,et al.  Large-scale read/write margin measurement in 45nm CMOS SRAM arrays , 2008, 2008 IEEE Symposium on VLSI Circuits.

[12]  Rajiv V. Joshi,et al.  Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[13]  Zheng Guo,et al.  SRAM stability characterization using tunable ring oscillators in 45nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[14]  D. Schmitt-Landsiedel,et al.  Analysis of Read Current and Write Trip Voltage Variability From a 1-MB SRAM Test Structure , 2008, IEEE Transactions on Semiconductor Manufacturing.

[15]  Zheng Guo,et al.  Characterization of Dynamic SRAM Stability in 45 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[16]  C. Radens,et al.  A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing , 2008, IEEE Journal of Solid-State Circuits.