Review paper on adaptive filters using VLSI
暂无分享,去创建一个
[1] Mihir Narayan Mohanty,et al. VLSI Design and Implementation for Adaptive Filter using LMS Algorithm , 2011 .
[2] M.Hosseinghadiry,et al. Two New Low Power High Performance Full Adders with Minimum Gates , 2009 .
[3] Neil Weste,et al. Principles of CMOS VLSI Design , 1985 .
[4] R. Ramya,et al. LOW-POWER AND LOW-AREA ADAPTIVE FIR FILTER BASED ON DISTRIBUTED ARITHMETIC AND LMS ALGORITHM , 2014 .
[5] Yousef Seifi Kavian,et al. FPGA implementation of LMS self correcting adaptive filter (SCAF) and hardware analysis , 2012, 2012 8th International Symposium on Communication Systems, Networks & Digital Signal Processing (CSNDSP).
[6] Stefania Perri,et al. A high-speed energy-efficient 64-bit reconfigurable binary adder , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[7] G. Ramana Murthy,et al. Design of Low Power and High Speed Digital IIR Filter in 45nm with Optimized CSA for Digital Signal Processing Applications , 2014 .
[8] Mónico Linares Aranda,et al. CMOS Full-Adders for Energy-Efficient Arithmetic Applications , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[9] Bart R. Zeydel,et al. Energy-Efficient Design Methodologies: High-Performance VLSI Adders , 2010, IEEE Journal of Solid-State Circuits.
[11] José Carlos Príncipe,et al. Analog hardware implementation of adaptive filter structures , 1997, Proceedings of International Conference on Neural Networks (ICNN'97).
[12] A. Chandra Shaker,et al. FPGA Optimized Low Power And High Speed FIR Filter Structures For DSP Applications , 2013 .
[14] Shrikant Patel. DESIGN AND IMPLEMENTATION OF 31-ORDER FIR LOW-PASS FILTER USINGMODIFIED DISTRIBUTED ARITHMETICBASED ON FPGA , 2013 .
[15] Yuan-Sun Chu,et al. A Low-Power Multiplier With the Spurious Power Suppression Technique , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[16] A. R. Shankar,et al. DESIGN AND IMPLEMENTATION OF VLSI SYSTOLIC ARRAY MULTIPLIER FOR DSP APPLICATIONS , 2013 .
[17] Paraskevas Kalivas,et al. New Systolic And Low Latency Parallel FIR Filter Schemes , .
[18] Sang Yoon Park,et al. Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.
[19] Rafi Ahamed Shaik,et al. High Performance Architecture for LMS Based Adaptive Filter Using Distributed Arithmetic , .
[20] John G. Proakis,et al. Digital Signal Processing: Principles, Algorithms, and Applications , 1992 .
[21] Area Efficient Fast Block LMS Adaptive Filter Using Distributed Arithmetic , 2013 .
[22] Edwin Hsing-Mean Sha,et al. A novel multiplexer-based low-power full adder , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.
[23] Bahram Rashidi,et al. Low Power FPGA Implementation of Digital FIR Filter Based on Low Power Multiplexer Base Shift/Add Multiplier , 2013 .
[24] K. Saranya. Low Power and Area-Efficient Carry Select Adder , 2013 .
[25] Sanu Mathew,et al. Comparison of high-performance VLSI adders in the energy-delay space , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[26] Keivan Navi,et al. Two New Low-Power and High-Performance Full Adders , 2009, J. Comput..
[27] Giorgos Dimitrakopoulos,et al. High-speed parallel-prefix VLSI Ling adders , 2005, IEEE Transactions on Computers.